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4
Table 4. ELECTRICAL CHARACTERISTICS (continued)
(T
A
= T
MIN
 to T
MAX
, V
DD
= 3.0 V to 3.6 V, unless otherwise noted) (Note 1)
Parameter
Unit
Max
Typ
Min
Test Conditions/Comments
SMBus Interface (See Figure 2)
Logic Input High Voltage, V
IH
STBY
, SCLK, SDATA
V
DD
= 3.0 V to 5.5 V
2.2


V
Logic Input Low Voltage, V
IL
STBY
, SCLK, SDATA
V
DD
= 3.0 V to 5.5 V


0.8
V
SMBus Output Low Sink Current
SDATA Forced to 0.6 V
6.0


mA
ALERT
 Output Low Sink Current
ALERT
 Forced to 0.4 V
1.0


mA
Logic Input Current, I
IH
, I
IL
1.0

+1.0
mA
SMBus Input Capacitance, SCLK, SDATA

5.0

pF
SMBus Clock Frequency


100
kHz
SMBus Clock Low Time, t
LOW
t
LOW
 between 10% Points
4.7


ms
SMBus Clock High Time, t
HIGH
t
HIGH
 between 90% Points
4.0


ms
SMBus Start Condition Setup Time,
t
SU:STA
4.7


ms
SMBus Repeat Start Condition
250


ns
Setup Time, t
SU:STA
Between 90% and 90% Points
250


ns
SMBus Start Condition Hold Time, t
HD:STA
Time from 10% of SDATA to 90% of SCLK
4.0


ms
SMBus Stop Condition Setup Time, t
SU:STO
Time from 90% of SCLK to 10% of SDATA
4.0


ms
SMBus Data Valid to SCLK
Time for 10% or 90% of SDATA to 10% of SCLK
250


ns
Rising Edge Time, t
SU:DAT
Time for 10% or 90% of SDATA to 10% of SCLK
250


ns
SMBus Data Hold Time, t
BUF:DAT
0


ms
SMBus Bus Free Time, t
BUF
Between Start/Stop Condition
4.7


ms
SCLK Falling Edge to SDATA


1
ms
Valid Time, t
VD:DAT
Master Clocking in Data


1
ms
1.  T
MAX
= 100癈, T
MIN
= 0癈
2.  Operation at V
DD
= 5.0 V guaranteed by design; not production tested.
3.  Guaranteed by design; not production tested.
Figure 2. Serial Bus Timing
STOP
START
t
SU; DAT
t
HIGH
t
F
t
HD; DAT
t
R
t
LOW
t
SU; STO
STOP  START
SCLK
SDATA
t
BUF
t
HD; STA
t
HD; STA
t
SU; STA
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